The present invention generally relates to the field of semiconductors, and more particularly relates to a method of fabricating source-drain contacts, and/or gate contact, on semiconductor structures.
Silicide/source-drain interface resistance is a major contributor to the total external parasitic resistance of a semiconductor contact. As the source-drain contact dimensions are aggressively scaled, it can increase variability in contact resistance within a CMOS device or between various devices. New semiconductor fabrication approaches are needed to reduce the variability in contact resistance.